Every input a chip needs, from design tools through wafer fabrication to final test, mapped as a global chain, then scored for what it would take to make it in India.
Nine stages, one shared 0 to 100 percent axis. Click a country to trace it top-to-bottom. Tap a row for its details and sources below.
Every leading-edge tape-out worldwide passes through one of Synopsys, Cadence, or Siemens EDA; new tape-outs stop within a quarter of any one of them halting service.
IBS "Design IP Market Share Report" 2025 paywalled Synopsys 10-K FY2025 Cadence 10-K FY2024
SIA "State of the U.S. Semiconductor Industry" 2024 BCG-SIA "Emerging Resilience in the Semiconductor Supply Chain" May 2024
Taiwan holds 92% of ≤7 nm capacity, but the honest chokepoint is TSMC alone (~85%). A TSMC-specific event removes almost all leading-edge output regardless of geography.
TrendForce Foundry Tracker Q1 2026 paywalled TSMC 20-F FY2024
China's ~50% share is the fastest-growing chokepoint on the map. Automotive, industrial, power and MCU chips (analog + RF) all sit here.
CSIS "China's Localization Drive in Semiconductors Gains Impetus from Allied Chip Export Controls" (Sujai Shivakumar) 2026 SEMI World Fab Forecast Feb 2025 paywalled USITC "Semiconductor Manufacturing: Industry Trends, Global Competition, Federal Policy" 2022
NL 82% understates the chokepoint. Every ASML EUV scanner depends on optics from Carl Zeiss SMT (Germany, sole source) and a CO₂ drive laser from Trumpf (Germany, sole source). A Zeiss stop-work removes 100% of new EUV capacity irrespective of ASML's output.
ASML Annual Report 2025 (Form 20-F) ASML supplier disclosure (Zeiss single-source status) Canon FY2024 Corporate Report Nikon FY2024 Annual Report
Five firms (Applied Materials, Lam, TEL, KLA, ASM International) supply most deposition, etch, CMP and inspection tools globally. US and Japanese controls on advanced-node WFE exports to China are the sharpest lever on Chinese leading-node ambition.
SIA "State of the U.S. Semiconductor Industry" 2024 VLSI Research WFE Market Share Mar 2025 paywalled Applied Materials 10-K FY2024 Lam Research 10-K FY2024 KLA 10-K FY2024 Tokyo Electron FY2024 Annual Report
Photoresist is a working-capital-thin, custom-formulated input. There is no strategic reserve; a JSR/TOK stop-work halts new wafer starts globally within weeks.
METI photoresist export-controls background paper SEMI Materials Market Report Q4 2024 paywalled JSR Corporation Annual Report FY2024
300 mm wafer capacity is a five-firm oligopoly; new fab construction lead time is 3-5 years. Japan alone holds more than half.
SEMI Silicon Manufacturers Group 2024 annual paywalled Shin-Etsu Chemical Annual Report FY2024 SUMCO Annual Report FY2024
Advanced packaging (CoWoS, SoIC, HBM stacks) is dominated by TSMC in-house, not by any OSAT — a separate concentration the top-10 revenue ranking does not capture. On the OSAT side proper, ASE + Amkor + JCET together take roughly 60% of the independent packaging pool.
TrendForce Top-10 OSAT Ranking Q1 2026 paywalled Yole Group "Status of the Advanced Packaging Industry" 2024 paywalled ASE Technology Holding 20-F FY2024 Amkor Technology 10-K FY2024 JCET Group Annual Report FY2024
Eight countries clustered by the shape of their leverage. Tap one to see what actually breaks if it goes offline. Not exhaustive: Malaysia and Vietnam hold real weight in packaging and test, Singapore in wafer fab equipment and Israel in design, and the small print at the bottom of the panel spells the coverage rule.
Tap a country to see the fact and what breaks.
TSMC alone makes roughly 65% of the world’s foundry output by revenue and about 90% of everything below 7 nanometres. UMC, VIS and PSMC add another slice of mature-node capacity on top.
What breaks: Roughly 90% of leading-node (≤7 nm) capacity. AI accelerators, high-end GPUs and flagship smartphone SoCs come off TSMC wafers; Samsung Foundry alone cannot absorb the load.
ASML is the sole manufacturer of EUV lithography scanners. Every chip below the 5-nanometre node passes through an ASML EUV tool; there is no second supplier anywhere.
What breaks: Every new EUV lithography scanner. There is no second manufacturer worldwide; the sub-5 nm chip pipeline cannot advance a node.
US firms hold roughly 85% of the EDA tools market (Synopsys, Cadence, Siemens EDA) and around half of global design-IP revenue. Applied Materials, LAM and KLA also anchor the deposition, etch and inspection tool markets.
What breaks: New chip tape-outs anywhere in the world. Every leading-edge design passes through Synopsys, Cadence or Siemens EDA; installed licences run out at the next refresh, and new WFE tool orders freeze on the same timeline.
Japan supplies roughly 90% of the world’s advanced photoresist (JSR, TOK, Shin-Etsu, Fujifilm) and about 55% of raw silicon wafers (Shin-Etsu, SUMCO). Most CMP slurries and specialty gases route through Japanese firms too.
What breaks: About 90% of advanced photoresist and 55% of raw silicon wafers. Front-end fabs everywhere run out of resist and fresh wafers within weeks; no strategic reserve exists.
Samsung and SK hynix together produce roughly 70% of the world’s DRAM and about half of NAND flash. Samsung Foundry also carries the largest slice of leading-edge capacity outside TSMC.
What breaks: About 70% of world DRAM and half of NAND. Phones, PCs and servers hit memory stockouts within weeks; Micron cannot backfill at that volume.
China holds roughly 35% of the world’s mature-node (28 nm and above) fab and back-end assembly capacity, is the largest single buyer of every input above, and dominates gallium, germanium and rare-earth feedstock.
What breaks: Global gallium, germanium and rare-earth feedstock. And the world loses its largest single buyer of chips: a demand shock hitting every seller at once.
Carl Zeiss SMT is the sole supplier of EUV optics to ASML; Trumpf is the sole supplier of the CO₂ laser drive. Losing Germany takes lithography with it, one step upstream of losing the Netherlands. Infineon and GlobalFoundries Dresden add power and RF capacity on top.
What breaks: Every ASML EUV scanner. Zeiss SMT is the sole EUV-optics supplier; Trumpf is the sole CO₂ laser drive. The litho chain stops one step upstream of losing the Netherlands.
India supplies roughly 20% of the world’s chip-design engineering labour to global fabless firms. The first commercial OSATs (Tata Assam, Micron Sanand, CG-Kaynes Sanand, HCL-Foxconn Jewar) are under construction and not yet at volume; there is no operating commercial fab.
What breaks: Nothing in the near term. Roughly 20% of global chip-design engineering hours re-route to other centres over multiple quarters; hardware supply is largely unaffected.
What continues: Back-end packaging (India, Malaysia, Vietnam), EDA tools (United States), memory (South Korea) and design IP (US, UK) all keep shipping.
Directory coverage: 1 of 96 inputs where Taiwan holds a majority of confirmed suppliers; 0 where Taiwan is the only confirmed supplier worldwide. The small number is a mapping gap, not a signal. Taiwan sits downstream (as a buyer or a fab) of the inputs this directory tracks.
TrendForce top-10 foundry revenue tracker ; TSMC 20-F FY2025
What continues: Mature-node fabs (28 nm and above) keep running on DUV lithography (also ASML, plus Canon and Nikon steppers). Advanced logic stops at the next tool refresh.
Directory coverage: 0 of 96 inputs where Netherlands holds a majority of confirmed suppliers; 0 where Netherlands is the only confirmed supplier worldwide. The small number is a mapping gap, not a signal. Netherlands sits downstream (as a buyer or a fab) of the inputs this directory tracks.
ASML Annual Report 2025 (Form 20-F) ; ASML supplier disclosure
What continues: Manufacturing continues on existing tool licences and installed base. New tape-outs, tool upgrades and IP refreshes stop within a quarter.
Directory coverage: 19 of 96 inputs where United States holds a majority of confirmed suppliers; 0 where United States is the only confirmed supplier worldwide.
Synopsys 10-K FY2025 ; Cadence 10-K FY2025 ; IBS design-IP market share report
What continues: Design, assembly and test continue on inventory. Front-end fabs everywhere run out of resist and fresh wafers within weeks.
Directory coverage: 15 of 96 inputs where Japan holds a majority of confirmed suppliers; 0 where Japan is the only confirmed supplier worldwide.
SEMI materials market report ; METI photoresist export-controls background paper
What continues: Logic manufacturing, EDA and packaging continue. Memory supply for phones, PCs and servers is what breaks; first stockouts show up in weeks.
Directory coverage: 0 of 96 inputs where South Korea holds a majority of confirmed suppliers; 0 where South Korea is the only confirmed supplier worldwide. The small number is a mapping gap, not a signal. South Korea sits downstream (as a buyer or a fab) of the inputs this directory tracks.
What continues: Advanced-node manufacturing outside China is unaffected. The demand-side shock hits every seller; feedstock substitutions take 12 to 24 months.
Directory coverage: 0 of 96 inputs where China holds a majority of confirmed suppliers; 0 where China is the only confirmed supplier worldwide. The small number is a mapping gap, not a signal. China sits downstream (as a buyer or a fab) of the inputs this directory tracks.
SEMI world fab forecast ; USGS mineral commodity summaries (gallium, germanium)
What continues: Same shape as losing the Netherlands: mature-node DUV production continues, advanced nodes stop.
Directory coverage: 3 of 96 inputs where Germany holds a majority of confirmed suppliers; 2 where Germany is the only confirmed supplier worldwide.
ASML supplier disclosure (Zeiss single-source status) ; Trumpf annual report FY2024/25
What continues: Global chip supply is largely unaffected in the near term. Design timelines at fabless firms slip on a multi-quarter horizon as work rebalances to other centres.
Directory coverage: 9 of 96 inputs where India holds a majority of confirmed suppliers; 0 where India is the only confirmed supplier worldwide.
NASSCOM ESDM talent report ; India Semiconductor Mission approved-project list
How to read this. The chokepoint type comes from the cited fact, not from our supplier row counts. A directory that measured itself would flatter itself; the coverage line above is a debug check, not a headline.
Twenty capabilities across four layers. Click any card to remove it. The cause turns red, anything that stops downstream turns grey, and anything that keeps running under strain shows yellow. Click a different card to try a different scenario.
Click any card to run a scenario.
Carl Zeiss SMT (Germany) · sole supplier
Sole source of the mirror stack that lets EUV work. No second supplier exists at any node.
Trumpf (Germany) · sole supplier
CO₂ drive laser for the tin-droplet plasma inside every ASML EUV scanner. No alternative in production.
JSR (Japan) ; Tokyo Ohka Kogyo (Japan) ; Shin-Etsu (Japan) ; Fujifilm (Japan)
Four Japanese firms hold ~89% of KrF/ArF/EUV resist between them.
SEMI materials market report ; METI photoresist export-controls background paper
Shin-Etsu (Japan) · ~30% ; SUMCO (Japan) · ~25% ; SK Siltron (South Korea) ; GlobalWafers (Taiwan) ; Siltronic (Germany)
Japan holds ~55% of 300 mm output; the two firms above lead a five-firm oligopoly.
Applied Materials (United States) ; Lam Research (United States) ; KLA (United States) ; Tokyo Electron (Japan)
Deposition, etch, CMP, inspection. Four firms hold ~80%; ASM International rounds out the top five.
VLSI Research WFE market share ; Applied Materials 10-K FY25
China (state-linked producers) (China) · ~80% Ga / ~60% Ge
Feedstock for compound-semi (GaN, GaAs), specialty magnets and some tool components. Not required for standard Si logic.
ASML (Netherlands) · sole supplier
Every chip below the 5 nm node passes through an ASML EUV tool. No second supplier anywhere.
Arm Holdings (SoftBank) (United Kingdom) · sole supplier of the ARM ISA
Sole licensor of the ARM ISA that runs almost every smartphone SoC. RISC-V is emerging but not drop-in.
Intel (United States) ; AMD (United States)
The two firms with a licence to design x86-64 chips. All PC/server CPUs above ARM run on this ISA.
ASML (Netherlands) ; Canon (Japan) ; Nikon (Japan)
Three suppliers. Mature-node fabs can requalify between them.
Synopsys (United States) ; Cadence (United States) ; Siemens EDA (United States)
The three US firms hold ~85% of the EDA market. Manufacturing continues on existing licences; new tape-outs stop within a quarter.
TSMC (Taiwan) · ~92% of ≤7 nm ; Samsung Foundry (South Korea) · ~8%
Intel Foundry is ramping 18A but not yet at meaningful external-customer volume.
Samsung (South Korea) ; SK hynix (South Korea) ; Micron (United States) ; CXMT (China) ; YMTC (China)
Samsung + SK hynix hold ~70% of DRAM; the two of them plus Micron dominate NAND outside China.
SMIC (China) ; GlobalFoundries (United States) ; UMC (Taiwan) ; TSMC (mature) (Taiwan)
Broadly substitutable across a dozen firms in five countries; VIS, PSMC and X-Fab add capacity outside the top four.
ASE (Taiwan) ; Amkor (United States) ; JCET (China) ; SPIL (ASE) (Taiwan)
Six major OSATs plus in-house packaging at TSMC and every IDM. Genuinely substitutable at the standard packaging tier.
NVIDIA, AMD, Apple, Qualcomm, MediaTek, Broadcom (fabless) (Multiple)
AI accelerators, high-end GPUs, smartphone SoCs. Rides the leading-foundry + EUV + advanced-resist chain.
Intel, AMD (x86); Apple, AWS Graviton, Ampere (ARM) (Multiple)
x86 dominant on Windows/legacy servers; ARM rising on Mac, hyperscaler and phone-class server SKUs.
Mercury Research CPU market share
Samsung, SK hynix, Micron (branded modules) (Multiple)
DRAM and NAND for phones, PCs, servers and data-centre storage.
TI, Infineon, STMicro, ADI, NXP, Renesas (Multiple)
Automotive, industrial, RF/5G, discretes. Runs on mature-node fabs; broadly substitutable.
IC Insights Analog / Power report
STMicro, NXP, Microchip, Renesas, Espressif (Multiple)
Smart devices, IoT endpoints, consumer white goods. Runs on mature-node fabs.
IHS/Omdia MCU market share
Ordered upstream to downstream, from design tools to finished-goods test.
96 inputs, tiered by India-buildability. Open a tier to browse. Within each tier, cheapest and fastest first. Each card still carries its vertical along the top.
Under roughly Rs 5 crore of entry capital and 12 to 24 months to a qualified first shipment. A founder can start here.
Contract engineering that makes a chip testable: inserting scan chains, compressing patterns and driving coverage up before the design is frozen.
Substation, standby generation, uninterruptible supply and power conditioning. A momentary sag scraps whatever is in process across the whole floor.
Garments, gloves, wipes, swabs and filters, consumed continuously by every person and every air handler in the building, on every shift, forever.
Contracted verification engineering. The largest single category of semiconductor work done in India by headcount, and the usual first hire for a new design team.
Turning ITI and diploma graduates into cleanroom operators and equipment technicians, the input every plant needs most and can buy least.
The adhesive film that holds a wafer together while it is cut, the steel frame that carries it, and the diamond blade doing the cutting.
Rigging tools into place, connecting them to facilities, qualifying them, and then keeping them running for the next fifteen years.
The formal programmes (AEC-Q for automotive, JEDEC for the rest) that a package and its supply chain must pass before a customer will accept the part.
The envelope itself: panels, ceiling grid, fan filter units, airlocks and the pressure regime that keeps particles out of an assembly floor.
Designing the substrate, the routing and the power delivery around a die, and proving by simulation that the package will not degrade the signals passing through it.
The printable solder-powder-and-flux mixture used to attach components, and the flux chemistry that strips oxide so the joint can wet properly.
Tested parts are loaded into carrier tape or trays, baked and sealed against moisture, and labelled for shipment. The last operation before the part leaves.
Firms that take a customer specification all the way to working packaged silicon, absorbing tool licences, IP procurement and foundry interface along the way.
The epoxy paste or adhesive film that bonds the die to its leadframe or substrate, and carries heat away from it.
The stainless piping, valve manifold boxes and cabinets that move gases and chemicals from the yard to the tool without contaminating them.
The tin-based plating chemistry applied to exposed leads for solderability and corrosion resistance, plus the associated etchants.
Floorplanning, placement, routing and timing closure delivered as a service. The most tool-dependent and most schedule-critical part of the design flow.
The compound is fully cross-linked in a batch oven, moulding flash is stripped from the leads, and the package is laser-marked with part, lot and date code.
The local machine shops that fabricate fixtures and spares, and keep packaging tools running. Cross-cutting across every process step.
The mechanical interface between a packaged part and the test head, plus the consumable parts an automated test line wears through.
The greases, gels and solder preforms that move heat from die to lid, and the metal heat spreader itself on any package that dissipates real power.
The solder interconnect of a flip-chip package and the resin that fills beneath the die to survive thermal cycling.
Moving regulated chemicals and temperature-sensitive materials into a landlocked state, and holding imported inputs under bond until they are consumed.
Water purified to a resistivity of 18.2 megohm-centimetre with organics and particles at parts-per-trillion. An assembly plant needs far less of it than a fab, but still needs it.
Parts are held at elevated voltage and temperature for hours or weeks to force out infant mortality, and stressed to characterise how the population ages.
The packaged part is exercised across its full electrical specification on automated test equipment, the operation that decides what actually ships.
Exposed leads are electroplated with a tin-based finish for solderability, then trimmed and formed to their final package geometry.
Bringing first silicon up on a bench, characterising it against specification, and writing the test programs the assembly line will later run in volume.
Precision-stamped or etched copper-alloy or iron-nickel-alloy sheet that carries the die and provides the electrical path outward.
There is real money here, but not in manufacturing the thing. The opening is in stocking, distribution, purity uplift or a licensed partnership.
Nitrogen and forming gas for inerting and reflow. An assembly plant’s gas requirement is far simpler than a wafer fab’s specialty stack.
Tools that design the substrate and board alongside the die, because at modern speeds the package is part of the circuit rather than a container for it.
Physics-based simulation of how a device will behave before anyone builds one: dopant diffusion, electric fields, breakdown voltage and thermal response.
Building and validating the process design kits that let designers target a fab at all: the models, rule decks and libraries that describe what the process can do.
Fine-drawn gold or copper wire that carries the electrical path from die pad to leadframe. Consumed continuously on every active wire-bond line.
The operation that lifts each die off the tape and bonds it to a leadframe or substrate at rates approaching 30,000 units an hour.
The robotics that present each part to the test head at temperature and sort it into bins afterwards. Throughput of the test cell is set here, not by the tester.
The filled epoxy transfer-moulded around the die to protect it. Rheology is formulation-specific to each package family, so it cannot be pooled.
Finished packages are separated from the moulded strip or matrix by saw or punch, the last mechanical operation before the part is tested.
Precisely sized tin-silver-copper spheres attached to the underside of a BGA package to form its board-level connections.
Cleaning, stripping, recoating and re-qualifying the wear parts that come out of process tools, plus holding the spares inventory the plant draws on.
Several die plus passives are assembled into a single package or module, the format Kaynes Semicon used for India’s first commercially packaged multi-chip parts.
A resin-bonded diamond blade spinning at 30,000 rpm cuts the wafer into individual die along its scribe lines. Still the volume workhorse.
The abrasive suspensions and polyurethane pads that do the actual planarisation. Consumed continuously and formulated per material being polished.
Filters, membranes, resins and purifiers that sit at the point of use on every chemical and gas line, catching what the supply chain missed.
Epoxy moulding compound is forced around the bonded die under heat and pressure in a multi-cavity tool, forming the black body of the package.
The robots, front-end modules, carriers and overhead transport that move wafers between tools without a human ever touching one.
Tools that flatten the wafer between layers by polishing it against a pad with an abrasive slurry, the process that makes multi-layer wiring possible.
The lab that establishes why a part failed: acoustic imaging for delamination, X-ray for voids, cross-sectioning and electron microscopy for everything else.
Vertical batch furnaces and single-wafer rapid thermal systems that oxidise, anneal and activate dopants at temperatures up to 1,100 degrees.
Hydrofluoric, sulphuric, nitric and phosphoric acids plus the solvent set, purified to SEMI grades where contamination is measured in parts per trillion.
Non-product wafers used to qualify tools and monitor processes, and the business of stripping and repolishing them so they can be used again.
The developers, anti-reflective coatings and edge-bead removers used with resist. Higher volume than the resist itself and considerably less exotic.
High-purity metal discs consumed by physical vapour deposition tools: copper, titanium, tantalum, tungsten and aluminium at five nines purity and above.
Treating plating and cleaning effluent to discharge standard, recovering metals where it pays, and in most Indian states discharging no liquid at all.
Vacuum systems that deposit metal films by knocking atoms off a solid target with plasma, how the copper, titanium and tantalum layers get onto the wafer.
Single-wafer and batch systems that strip particles, organics and metal contamination between every other process step. A wafer is cleaned dozens of times.
Glass panels with through-vias replacing organic laminate as the package core: flatter, thermally better matched to silicon, and the subject of India’s Odisha bet.
The quartz plates carrying the patterns a scanner projects onto the wafer. A leading-edge mask set costs more than most factories.
Wide-bandgap substrates for high-voltage power devices. Harder to grow than silicon, far more valuable per wafer, and where India has actually committed money.
Requires a joint venture, a technology licence, or a multinational’s balance sheet. Worth understanding, not worth starting.
Software that inserts test structures into a design and generates the patterns that will exercise them, deciding how testable the finished chip is.
The standard cell libraries, memory compilers and input-output cells every digital chip is built from. Invisible, unglamorous, and impossible to design without.
Turning a finished layout into the data a mask writer can use, correcting for the optical distortions of the exposure and fracturing the result into writeable shapes.
Organometallic compounds that decompose on a hot wafer to leave behind a film, the chemistry that makes high-k gates and atomic-layer films possible.
Gallium arsenide, indium phosphide, sapphire and germanium, the substrates behind optical transceivers, lasers, LEDs and specialist RF.
The copper baths and organic additive packages that fill damascene trenches and vias without voids. The additives are the product; the copper sulphate is not.
Incoming wafers are received, inspected and mounted onto a tape-and-frame carrier so they can survive every subsequent handling step.
Die are stacked vertically and joined copper-to-copper without solder, giving interconnect densities two orders of magnitude beyond microbumps.
Schematic capture, circuit simulation and hand layout for the analog and mixed-signal blocks that cannot be synthesised from code.
The system that spins resist onto the wafer, bakes it, hands it to the scanner and develops it afterwards. Physically bolted to the scanner and sold as a pair.
Reactors that grow dielectric and metal films from gas-phase precursors: chemical vapour deposition in bulk, atomic layer deposition one monolayer at a time.
Phosphine, arsine, diborane and boron trifluoride: the sources of the impurity atoms that make silicon into a semiconductor. Among the most toxic materials in industry.
Argon fluoride, krypton fluoride and i-line systems that pattern everything from 7nm down-rev layers to the mature nodes India is actually building.
Silicon refined to eleven nines purity, one impurity atom in a hundred billion. The raw material every silicon device on earth begins as.
A prime wafer with a thin, precisely doped single-crystal layer grown on top, required by most power devices, image sensors and advanced CMOS.
The single-supplier machine that patterns every leading-edge chip, using 13.5nm light generated by vaporising tin droplets with a laser.
Die are reconstituted onto a carrier and a redistribution layer is built directly over them, eliminating the package substrate entirely.
The bumped die is placed face-down onto its substrate and the joints are formed, either by mass reflow through an oven or by thermocompression bonding one die at a time.
Solder balls or copper pillars are plated onto the wafer while it is still whole, so the die can later be flipped and soldered face-down onto its substrate.
Proving a design does what the specification says before committing to a mask set. Consumes more engineering hours than design itself on most modern chips.
Gallium nitride grown on silicon, silicon carbide or sapphire, the material behind fast chargers, RF power amplifiers and the next tier of power conversion.
The analog blocks that move data on and off a chip. Node-specific, brutally hard to design, and the reason most SoC teams license rather than build.
Multiple die are mounted side by side on a silicon or organic interposer carrying dense wiring and through-vias, the packaging behind every AI accelerator.
Particle accelerators that fire dopant ions into the silicon lattice at controlled energy and dose, defining where the device conducts and where it does not.
Bladeless singulation: a focused laser fractures the wafer internally, or a plasma etch cuts the streets, for die too thin or too fragile to saw.
The tools that turn register-transfer-level code into a manufacturable layout. The most concentrated software dependency in the chip industry.
The tools that measure whether every other tool did its job: critical dimensions, overlay, film thickness and the defects nobody intended to make.
The multi-layer laminate a flip-chip or BGA die is mounted on. The most expensive single item in most advanced packages, and the longest lead time.
The light-sensitive polymer that records the circuit pattern. Formulated per node and per tool, and made almost entirely in Japan.
Reactors that remove material with chemically reactive plasma, translating the pattern in the resist into the actual structure of the device.
Monocrystalline ingots pulled from molten silicon, sliced, lapped and polished into the mirror-flat discs every fab starts with.
Licensed, pre-verified processor designs. Almost no chip company designs its own CPU from scratch, which makes this one of the chain’s quietest chokepoints.
Nitrogen trifluoride, silane, tungsten hexafluoride and the halogen set: the reactive gases that etch and deposit, most of them dangerous.
A filled epoxy is drawn into the gap under a flip-chip die and cured, so thermal stress is carried by the encapsulant rather than by the solder joints.
The wafer backside is ground away to reduce a 775-micron substrate to a package-compatible thickness, sometimes below 50 microns for stacked die.
Every die is tested while still on the wafer, so failures are mapped and discarded before any packaging cost is spent on them.
Fine gold, copper or silver wire is welded from the die pad to the package lead by heat, pressure and ultrasonic energy, still the majority of all interconnects made.
How this is maintained. Curated and versioned, not scraped. Every entry carries a review date, and an import-dependency figure cannot be published without a stated basis; the build rejects it. Supplier listings document the market as we understand it and are not endorsements. Every vertical and entry page defines its own terms and confidence labels directly beside the data they describe.