Logic Synthesis and Place-and-Route
The tools that turn register-transfer-level code into a manufacturable layout. The most concentrated software dependency in the chip industry.
TierC
Imported Not established
EntryNot MSME
Qualify30+ mo
EDA and Semiconductor IP
The tools and licensed blocks a chip is designed with.
Nothing is fabricated before it is designed, and almost nothing is designed from scratch. This vertical covers the design automation software and the pre-verified IP blocks that every modern chip is assembled from.
Talent: The narrowest talent funnel in the chain. India has depth in verification and physical design services but very little in EDA tool development itself.
What these figures mean
- Import dependency
- The share of Indian demand for this input that is met by imports today. A percentage is published only where we can state the basis for it, and the build rejects a figure that has none. “Not established” means no sourced figure exists yet, not that the figure is zero; for the domestic picture, read “Made in India today” instead.
- Made in India today
- How much of this input is actually produced in India: none, pilot scale, partial, or established. This is the field to read when import dependency is not established.
- MSME entry capital
- What it would plausibly cost an Indian MSME to enter this input at the smallest viable scale, in crore rupees. Plant and equipment only; it excludes working capital and the qualification cycle.
- Time to qualify
- How long from a working sample to a qualified first shipment, once the line exists. Qualification, not construction, is what usually decides whether an entry succeeds.
- India readiness tier
- Our verdict on whether an Indian founder can realistically enter this input, derived from the four figures above and stated as one of three tiers.
The three tiers
- Tier A: Buildable Now
- Under roughly Rs 5 crore of entry capital and 12 to 24 months to a qualified first shipment. A founder can start here.
- Tier B: Partnership or Distribution
- There is real money here, but not in manufacturing the thing. The opening is in stocking, distribution, purity uplift or a licensed partnership.
- Tier C: Not Yet
- Requires a joint venture, a technology licence, or a multinational’s balance sheet. Worth understanding, not worth starting.
Made in India today
- None
- No Indian production we can identify. Demand is met entirely from abroad.
- Pilot scale
- Made in India at laboratory, pilot-line or single-customer scale only.
- Partial
- Real Indian production exists, but it covers part of the range or part of the demand.
- Established
- Indian production is routine and qualified, at commercial volume.
9 entries
Functional Verification and Simulation
Proving a design does what the specification says before committing to a mask set. Consumes more engineering hours than design itself on most modern chips.
TierC
Imported Not established
EntryNot MSME
Qualify30+ mo
Analog and Custom IC Design Tools
Schematic capture, circuit simulation and hand layout for the analog and mixed-signal blocks that cannot be synthesised from code.
TierC
Imported Not established
EntryNot MSME
Qualify30+ mo
Processor IP Cores
Licensed, pre-verified processor designs. Almost no chip company designs its own CPU from scratch, which makes this one of the chain’s quietest chokepoints.
TierC
Imported Not established
EntryNot MSME
Qualify30+ mo
Interface and SerDes PHY IP
The analog blocks that move data on and off a chip. Node-specific, brutally hard to design, and the reason most SoC teams license rather than build.
TierC
Imported Not established
EntryNot MSME
Qualify30+ mo
DFT and ATPG Tools
Software that inserts test structures into a design and generates the patterns that will exercise them, deciding how testable the finished chip is.
TierC
Imported Not established
Entry<Rs 1.5 Cr
Qualify6–12 mo
TCAD and Process Simulation
Physics-based simulation of how a device will behave before anyone builds one: dopant diffusion, electric fields, breakdown voltage and thermal response.
TierB
Imported Not established
Entry<Rs 1.5 Cr
Qualify6–12 mo
Package and PCB Co-Design Tools
Tools that design the substrate and board alongside the die, because at modern speeds the package is part of the circuit rather than a container for it.
TierB
Imported Not established
Entry<Rs 1.5 Cr
Qualify6–12 mo
Foundation and Memory IP
The standard cell libraries, memory compilers and input-output cells every digital chip is built from. Invisible, unglamorous, and impossible to design without.
TierC
Imported Not established
Entry<Rs 1.5 Cr
Qualify12–18 mo